Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
IEEE Transactions on Computers
Efficient embeddings of trees in hypercubes
SIAM Journal on Computing
The network architecture of the Connection Machine CM-5 (extended abstract)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
Embedding of Complete Binary Trees into Meshes with Row-Column Routing
IEEE Transactions on Parallel and Distributed Systems
Design of fault-tolerant distributed memory multiprocessors
Design of fault-tolerant distributed memory multiprocessors
The quest for petascale computing
Computing in Science and Engineering
The Combinatorics of Network Reliability
The Combinatorics of Network Reliability
Deadlock- and Livelock-Free Routing Protocols for Wave Switching
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Determining the Expected Load of Dynamic Tree Embeddings in Hypercubes
ICDCS '97 Proceedings of the 17th International Conference on Distributed Computing Systems (ICDCS '97)
Optimal task execution times for periodic tasks using nonlinear constrained optimization
The Journal of Supercomputing
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We present a real-time fault-tolerant design for an l-level k-ary tree multiprocessor and examine its reconfigurability. The k-ary tree is augmented by spare nodes and spare links. By utilizing the capabilities of wave-switching communication modules of the spare nodes, faulty nodes and faulty links can be tolerated. We consider two modes of operations. In the strict mode, the multiprocessor is under heavy computation or hard deadline and therefore we use a fast and local reconfiguration scheme to tolerate the faulty nodes. In the relaxed mode, where light computation or soft deadline is encountered, a global reconfiguration scheme is used to maximize the utilization of spare nodes, both in this mode as well as in the next strict mode. Both theoretical and simulation results are examined. Our simulation results, in the relaxed mode of operation, reveal that our approach can tolerate significantly more faulty nodes than other approaches, with a low overhead and no performance degradation.