A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
IEEE Transactions on Computers
On Implementing Large Binary Tree Architectures in VLSI and WSI
IEEE Transactions on Computers
A VLSI tree machine for relational data bases
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Computational Aspects of VLSI
Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures
IEEE Transactions on Computers
An Efficient Dictionary Machine Using Hexagonal Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship
IEEE Transactions on Computers
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The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for monolithic implementation of a large binary tree architectures. For board level multichip designs, a hybrid scheme, combining the new design with the SOFT approach, is presented. It shows better reliability than either design alone.