An Efficient Unsorted VLSI Dictionary Machine
IEEE Transactions on Computers
IEEE Transactions on Computers
On Implementing Large Binary Tree Architectures in VLSI and WSI
IEEE Transactions on Computers
Dictionary machines with a small number of processors
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Area-efficient vlsi computation
Area-efficient vlsi computation
A Generalized Simultaneous Access Dictionary Machine
IEEE Transactions on Parallel and Distributed Systems
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Several designs are presented for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The initial design objectives included: (1) single-cycle operability of host-issued modify and query commands (no compress instructions), (2) complete processor utilization (no waste processors), and (3) optimal 2 log n response times, where n is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously. They were forced to abandon objective (3), instead achieving a slightly weaker objective, namely, near-optimal (2 log n+R) response times, where R is the time for a round trip through the particular prenetwork used to connect the host to the roots of the query trees in the logarithmic network. Both sorted and unsorted versions of dictionary machines are presented. Those with orthogonal command networks achieve all objectives; those without orthogonal networks achieve only the first and third.