On Implementing Large Binary Tree Architectures in VLSI and WSI
IEEE Transactions on Computers
Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems
IEEE Transactions on Computers
Built-In Testing of Integrated Circuit Wafers
IEEE Transactions on Computers
Programmable Multichip Modules
IEEE Micro
Diagnosable Systems for Intermittent Faults
IEEE Transactions on Computers
| Hi-index | 0.00 |
Defining a dual role for spare processing elements (PEs) in reliability-challenged processing arrays is the major focus of the paper. The paper also explores a practical way to include reconfiguration hardware in single-package arrays. The implementation of array processor systems may include spare PE's for fault tolerance. These systems typically require a host for fault diagnosis, while the healthy spares sit idle. It is proposed to utilize the idling spare PEs for purposes of fault diagnosis, giving the array the capability of self diagnosis. Fault tolerance must incorporate additional hardware for reconfiguration, and existing plans have not found widespread use in single-package systems due to the extra cost and extra real estate. Multichip modules (MCMs) have the potential to offer fault tolerance with no increase in primary circuit area. It is proposed to contain the reconfiguration hardware in the active substrate of a silicon-based MCM. Further, the switches required for spares coverage can aid in the job of comparison based self-testing. We offer a complete solution to fault-tolerant arrays in the sense that diagnosis, reconfiguration and switching details are all addressed.