High-speed interpolation architecture for soft-decision decoding of Reed-Solomon codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reduced complexity interpolation architecture for soft-decision reed-solomon decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Backward interpolation architecture for algebraic soft-decision reed-solomon decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved decoding of Reed-Solomon and algebraic-geometry codes
IEEE Transactions on Information Theory
Algebraic soft-decision decoding of Reed-Solomon codes
IEEE Transactions on Information Theory
Algebraic Soft-Decision Decoding of Reed–Solomon Codes Using Bit-Level Soft Information
IEEE Transactions on Information Theory
Algebraic soft-decision decoder architectures for long Reed-Solomon codes
IEEE Transactions on Circuits and Systems II: Express Briefs
Unified architecture for Reed-Solomon decoder combined with burst-error correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reed-Solomon (RS) codes are used as error-correcting codes in numerous digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the iterative bit-level generalized minimum distance (BGMD) decoding can achieve similar or higher coding gain with lower complexity. The interpolation is a major step of ASD. The maximum achievable speed of this step is limited by the inherent serial nature of the interpolation algorithm. In this paper, a novel interpolation scheme that is capable of combining multiple interpolation iterations, as well as sharing interpolation results from previous decoding iterations, is developed for the iterative BGMD decoding. In addition, efficient VLSI architectures are proposed to implement the developed scheme. Based on the proposed architectures, an interpolator for a (255, 239) RS code is implemented on field programmable gate array (FPGA) devices. On a Xilinx Virtex-II device, our interpolator can achieve a throughput of 440 Mbps, which is 64% higher than the fastest previous design, with 51% less FPGA resource.