FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A Multi-Standard SDR Base Band Platform
ICCNMC '03 Proceedings of the 2003 International Conference on Computer Networks and Mobile Computing
A Tier 3 Software Defined AM Radio
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
Digital Systems Design Using VHDL
Digital Systems Design Using VHDL
Verilog® hdl: a guide to digital design and synthesis, second edition
Verilog® hdl: a guide to digital design and synthesis, second edition
Software radio: a modern approach to radio engineering
Software radio: a modern approach to radio engineering
Fundamentals of Digital Logic with Verilog Design
Fundamentals of Digital Logic with Verilog Design
RWS'09 Proceedings of the 4th international conference on Radio and wireless symposium
Recent developments in enabling technologies for software defined radio
IEEE Communications Magazine
A software-defined communications baseband design
IEEE Communications Magazine
Software-defined radio receiver: dream to reality
IEEE Communications Magazine
The software radio architecture
IEEE Communications Magazine
Architectural overview of the SPEAKeasy system
IEEE Journal on Selected Areas in Communications
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Some wireless communication systems must be able to receive and process signals from multiple source stations simultaneously. A common practice is to use multiple duplicated hardware resources; a different set of resources for each received station. A new coherent amplitude modulated (AM), time-division multiplexed (TDM), receiver system architecture and design, based on the software-defined radio (SDR) standard, is proposed, developed and validated via simulation and experimental hardware prototype testing. The new receiver system architecture and approach enables reception and processing of signals from multiple stations using the hardware resources normally needed for reception and processing of only one station. Production models of the proposed receiver/processing system architecture and design would be implemented in programmable-logic-device (PLD) technology [field-programmable-gate-array (FPGA) in our case] to accommodate rapidly changing communication protocols and standards and to enhance processing performance.