A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio

Authors:
Oliver Faust;Bernhard Sputh;Darran Nathan;Sana Rezgui;Andreas Weisensee;Alastair Allen
Affiliations:
-;-;-;-;-;-
Venue:
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Year:
2003

Citing 0
Cited 3

Modular software-defined radio

EURASIP Journal on Wireless Communications and Networking
A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform

IEICE - Transactions on Information and Systems
A new multichannel, coherent amplitude modulated, time-division multiplexed, software-defined radio receiver architecture, and field-programmable-gate-array technology implementation

IEEE Transactions on Signal Processing

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Abstract

Software Defined Radio (SDR) technology seeks to solve the problem of multiple incompatible broadcast/telecom standards available in different locations, by having standard specific processing defined in software. This software will be downloaded and run on generic hardware, so that different broadcast/telecom standards can be supported by downloadingcorresponding software modules. Computing platform based SDR attempts to bridge the worlds of computing and broadcast/telecoms, by exposing the features and resources of computers to SDR and vice versa. However, such a concept results in certain architectural issues that need to be resolved. This paper describes the concept of Computing Platform based SDR, and the resulting issues & desired features of such a system. An innovative system architecture that involves the supervised partial self-reconfiguration of a single FPGA isproposed and detailed. Finally, a system test is conducted to illustrate and verify the reconfiguration operation.