Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
The Panasas ActiveScale Storage Cluster: Delivering Scalable High Bandwidth Storage
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Power provisioning for a warehouse-sized computer
Proceedings of the 34th annual international symposium on Computer architecture
Thermal-aware task scheduling at the system software level
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Measurement and analysis of TCP throughput collapse in cluster-based storage systems
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
PortLand: a scalable fault-tolerant layer 2 data center network fabric
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
VL2: a scalable and flexible data center network
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
Safe and effective fine-grained TCP retransmissions for datacenter communication
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
A scalable micro wireless interconnect structure for CMPs
Proceedings of the 15th annual international conference on Mobile computing and networking
The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines
The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines
Proceedings of the ACM SIGCOMM 2010 conference
A case for guarded power gating for multi-core processors
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Abstraction and microarchitecture scaling in early-stage power modeling
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
IEEE Transactions on Computers
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The soaring power dissipation of computing infrastructures has effectively become a key performance bottleneck. At the same time, thermal issues arising from power hungry devices result in compromising reliability of such systems. At present, the processor cores within a chip multiprocessor (CMP) are interconnected using on-chip networks. At the same time, the emerging era of cloud computing and the associated large-scale distributed computing model are stretching the limits of computer networking. Hence, as an essential and pervasive fabric that binds all computing machinery, there is an underlying network that appears with varying scale and characteristics. In this paper, we take a look at methodologies for better management of the power budget across the cross-section of computing systems traversing the boundary between micro-level on-chip networks to macro-level cloud computing. We discuss methodologies for power and thermal management both at micro and macro scales and explore the role of one in reducing the power budget of the other.