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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Low power consumption and high-performance are the most important factors in modern embedded System-on-Chip (SoC) designs. Increasing computation complexity and incessant growth of clock frequency reveals the necessity for dynamic and smart utilization of the available hardware resources. The paper presents the modified LEON3 processor IP core as an exemplary process of enhancing single issue general purpose processor with superscalar abilities and low-power features. The results of this work can be applied to many existing general purpose processor models to achieve low-power and high-performance systems suitable for modern embedded applications. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle and dynamically manage incorporated power domains. The Enhanced LEON3 IP core was synthesized for 500MHz using UMC 90nm CMOS technology. Performed gate level VCD-based (Value Change Dump) power estimation shows that combining superscalar and low-power techniques allows performing faster program execution with less energy consumption than the original design.