Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Device Physics Impact on Low Leakage, High Speed DSP Design Techniques
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
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With technology scaling to deep submicron region, leakage power becomes dominant. With technology scaling, lower supply voltages are required to limit active power dissipation, excessive electric field & gate oxide leakage. Threshold voltage scaling has reached to a limit. Low threshold voltage results in excessive leakage [1]. Apart from device level tailoring, circuit design efforts are ongoing for leakage reduction in standby as well as active mode. We are presenting a methodology for reduced leakage databus which uses split supply rails. Compared to conventional power down methods, scheme is better in terms of leakage reduction, noise margin & reactivation time. Scheme is useful for long datalines particularly used in SOCs.