Design of an ultra low leakage buffer chain
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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The limitations of implementing low leakage schemes and their application to current state of the art components is discussed. In addition to source subthreshold leakage, both gate induced diode leakage current and tunneling gate leakage current must be comprehended. A viable leakage reduction strategy requires extensive modeling of circuits in the standby mode as well as new demands on the understanding of transistor physics. The ramifications of the physics of the behavior of transistors under conditions of high electric fields apply not only at the circuit level but can also impact the chip level system. In the coming applications of mobile electronics, understanding of this concept is critical.