The Stanford Dash Multiprocessor
Computer
Design patterns: elements of reusable object-oriented software
Design patterns: elements of reusable object-oriented software
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Using the SimOS machine simulator to study complex computer systems
ACM Transactions on Modeling and Computer Simulation (TOMACS)
FLASH vs. (Simulated) FLASH: closing the simulation loop
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Journal of Parallel and Distributed Computing
A Simple Simulator for Multicomputer Routing Networks
A Simple Simulator for Multicomputer Routing Networks
On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A first glance at Kilo-instruction based multiprocessors
Proceedings of the 1st conference on Computing frontiers
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism
Proceedings of the 31st annual international symposium on Computer architecture
Evaluating kilo-instruction multiprocessors
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
High-performance adaptive routing for networks with arbitrary topology
Journal of Systems Architecture: the EUROMICRO Journal
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks
IEEE Transactions on Parallel and Distributed Systems
Reducing the Interconnection Network Cost of Chip Multiprocessors
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
The modeling power of CINSim: Performance evaluation of interconnection networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
HPPNetSim: a parallel simulation of large-scale interconnection networks
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
Interconnection network simulation using traces of MPI applications
International Journal of Parallel Programming
Full-system simulation of distributed memory multicomputers
Cluster Computing
A system-level design methodology for application-specific networks-on-chip
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
A scalable organization for distributed directories
Journal of Systems Architecture: the EUROMICRO Journal
DART: a programmable architecture for NoC simulation on FPGAs
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
NoCs Simulation Framework for OMNeT++
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Evaluation of low-overhead organizations for the directory in future many-core CMPs
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
INSEE: an interconnection network simulation and evaluation environment
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Improving coherence protocol reactiveness by trading bandwidth for latency
Proceedings of the 9th conference on Computing Frontiers
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An environment has been developed which is capable of determining the impact that a multiprocessor interconnection subsystem causes on real application execution time. A general-purpose interconnection network simulator, called SICOSYS, able to capture essential aspects of the low-level implementation, has been integrated into two execution driven simulators for multiprocessors: RSIM and SimOS. The enhancement of both tools allows the analysis of new proposals for the interconnection subsystem of a cc-NUMA machine, from the VLSI level up to the real application level. Any new proposal can be translated to a specific message router architecture and by using a low-level implementation tool, the parameter delays of a detailed router model to be used by SICOSYS can be obtained.