An efficient dynamically reconfigurable on-chip network architecture

Authors:
Mehdi Modarressi;Hamid Sarbazi-Azad;Arash Tavakkol
Affiliations:
Sharif University of Technology, Tehran, Iran;Sharif University of Technology, Tehran, Iran and IPM School of Computer Science, Tehran, Iran;IPM School of Computer Science, Tehran, Iran
Venue:
Proceedings of the 47th Design Automation Conference
Year:
2010

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Abstract

In this paper, we present a reconfigurable architecture for NoCs on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications at run-time. The run-time topology construction mechanism involves monitoring the network traffic and changing the inter-node connections in order to reduce the number of intermediate routers between the source and destination nodes of heavy communication flows. This mechanism should also preserve the NoC connectivity. In this paper, we first introduce the proposed reconfigurable topology and then address the problem of run-time topology reconfiguration. Experimental results show that this architecture effectively improves the NoC power and performance over the existing conventional architectures.