Reducing Packet Dropping in a Bufferless NoC
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
An efficient dynamically reconfigurable on-chip network architecture
Proceedings of the 47th Design Automation Conference
A hybrid packet-circuit switched on-chip network based on SDM
Proceedings of the Conference on Design, Automation and Test in Europe
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
Energy-optimized on-chip networks using reconfigurable shortcut paths
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
APCR: an adaptive physical channel regulator for on-chip interconnects
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
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On-chip networks are the answer to the growing demands for high communication performance of chip multiprocessors.These networks have a number of characteristics that make their design quite different to off-chip networks. In particular,wires are an abundant available resource inside the chip. In this paper, we explore how to organize the huge wiring capabilities availablein on-chip networks. In particular, we analyze the option of distributing the wires among several parallel links connecting the same two switches.This technique is known as Space Division Multiplexing (SDM). The number of parallel sub-links and their width are two key parameters that are studied together with the relationship with the mean packet size.The paper shows that SDM is a technique to take into account in on-chip networks since it allows to highly increase the network accepted trafficat the expense of a small latency increase or even no increase. Moreover, in some networks, it allows to reduce the network hardware, providing similar performance results,which results in a reduction in the consumption of area and power.