Resource Deadlocks and Performance of Wormhole Multicast Routing Algorithms
IEEE Transactions on Parallel and Distributed Systems
A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes
IEEE Transactions on Computers
Deadlock-Free Multicast Wormhole Routing in 2-D Mesh Multicomputers
IEEE Transactions on Parallel and Distributed Systems
Multi-address Encoding for Multicast
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
SPDP '96 Proceedings of the 8th IEEE Symposium on Parallel and Distributed Processing (SPDP '96)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Connection-oriented Multicasting in Wormhole-switched Networks on Chip
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Fault-Tolerant Flow Control in On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Power-efficient tree-based multicast support for networks-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high bandwidth and scalability in on-chip networks, a newly added multicast capability can further enhance the performance by reducing the network load and facilitate coherence protocols of many-core CMPs [10]. This paper proposes a novel multicast router with dynamic packet fragmentation in on-chip networks. Packet fragmentation is performed to avoid deadlock in blocking situations, releasing the hold of an output virtual channel (VC) and allowing another packet to use the freed VC. From circuit simulation of the design implemented with IBM 90nm technology, the proposed router reduces latency by 38.6% and consumes 9% less energy than a unicast baseline router at the baseline saturation.