Parallel Testing of Multi-port Static Random Access Memories for BIST
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
On-Line Testing Scheme for Clock's Faults
Proceedings of the IEEE International Test Conference
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Support for Debugging in the Alpha 21364 Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ITC '02 Proceedings of the 2002 IEEE International Test Conference
High Speed and Highly Testable Parallel Two-Rail Code Checker
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Elimination of Traditional Functional Testing of Interface Timings at Intel
ITC '04 Proceedings of the International Test Conference on International Test Conference
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We analyze the risks associated with faults affecting some common Design For Testability (DFT) features employed within digital products. We will show that some DFT structures may become useless, with consequent dramatic impact on test effectiveness and product quality. We borrow the Fault Secure property and we will show that it guarantees that no escapes or false acceptance of faulty products may occur because of faults within the DFT structures.