Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Managing verification error traces with bounded model debugging
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Hi-index | 4.10 |
Due to increasing semiconductor design complexity, more errors are escaping presilicon verification and being discovered only after manufacturing. As an alternative to traditional manual chip repair, the authors propose the FogClear methodology, which automates the postsilicon debugging process and thereby reduces IC development time and costs.