The Superscalar Architecture of the MC68060

Authors:
Joe Circello;Greg Edgington;Dan McCarthy;James Gay;David Schimke;Steven Sullivan;Richard Duerden;Chris Hinds;Danny Marquette;Lal Sood;Al Crouch;Daniel Chow
Affiliations:
-;-;-;-;-;-;-;-;-;-;-;-
Venue:
IEEE Micro
Year:
1995

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Abstract

Motorola's MC68060 microprocessor is the newest member of the 68000 microprocessor family, its cost-effective and power-thrifty solution for high performanceembedded processing applications. This article focuses on the MC68060 microarchitecture features, such as its superscalar pipeline implementation, that enable it to achieve its high performance objectives while maintaining 68000 user code compatibility. The first MC68060 implementations, supplied at 50 MHz and 66 MHz, are 3.3V parts that achieve 103 dhrystone mips performance (66MHz).