Test Research in Japan

Authors:
Hideo Fujiwara;Yuzo Takamatsu;Takashi Nanya;Teruhiko Yamada;Hideo Tamamoto;Kiyoshi Furuya
Affiliations:
-;-;-;-;-;-
Venue:
IEEE Design & Test
Year:
1988

Citing 5
Cited 1

Built-In Testing of Memory Using an On-Chip Compact Testing Scheme

IEEE Transactions on Computers
A note on strongly fault-secure sequential circuits

IEEE Transactions on Computers
On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic

IEEE Transactions on Computers
On error indication for totally self-checking systems

IEEE Transactions on Computers
Error Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors

IEEE Transactions on Computers

Design and Test in Asia: More to Sample

IEEE Design & Test

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Abstract

Surveys recent research activities in test technology for computers, focusing on the results of university researchers. They cover test-pattern generation, fault simulation, design for testability, built-in self-test, and self-checking.