Fault analysis for computer memory systems and combinatorial logic networks
Fault analysis for computer memory systems and combinatorial logic networks
Fault location in memory systems by program
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers
An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories
IEEE Transactions on Computers
Failure diagnosis on the LT1280
IBM Journal of Research and Development
| Hi-index | 14.99 |
This correspondence presents an optimal algorithm to detect any single stuck-at-1 (s-a-1), stuck-at-0 (s-a-0) fault in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2nmemory accesses.