Using satisfiability in application-dependent testing of FPGA interconnects

Authors:
Mehdi Baradaran Tahoori
Affiliations:
Stanford University
Venue:
Proceedings of the 40th annual Design Automation Conference
Year:
2003

Citing 6
Cited 1

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Efficient conflict driven learning in a boolean satisfiability solver

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ITC '00 Proceedings of the 2000 IEEE International Test Conference
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FPGA Bridging Fault Detection and Location via Differential I{DDQ}

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

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Abstract

In this paper, a new technique for testing the interconnects of an arbitrary design mapped into an FPGA is presented. In this technique, only the configuration of logic blocks used in the design is changed. The test vector and configuration generation problem is systematically converted to a satisfiability (SAT) problem, and state of the art SAT-solvers are exploited for test configuration generation. Experimental results on various benchmark circuits show that only two test configurations are required to test for all bridging faults, achieving 100% fault coverage, with respect to the fault list.