BIST-Based Delay-Fault Testing in FPGAs

Authors:
Miron Abramovici;Charles Stroud
Affiliations:
-;-
Venue:
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Year:
2002

Citing 0
Cited 7

Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

Journal of Electronic Testing: Theory and Applications
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Journal of Electronic Testing: Theory and Applications
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults

Journal of Electronic Testing: Theory and Applications
Online BIST and BIST-based diagnosis of FPGA logic blocks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

We present the first delay-fault testing approach for FPGAs, applicable both for manufacturing and for on-line testing. Our approach is based on BIST, is comprehensive, and does not require expensive ATE. We have successfully implemented this BIST approach on the ORCA2C series FPGA.