Application-Dependent Testing of FPGA Interconnects

Authors:
Mehdi Baradaran Tahoori
Affiliations:
-
Venue:
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2003

Citing 0
Cited 3

Fault tolerance of switch blocks and switch block arrays in FPGA

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-dependent testing of FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fine grain faults diagnosis of FPGA interconnect

Microprocessors & Microsystems

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Abstract

A new technique is presented for testing all possible faults in the interconnects of an arbitrary design implemented into an FPGA. The fault list includes all bridging faults between all pairs of nets in the design, as well as multiple stuck-at and open faults. Test configurations are obtained by just modifying the configuration of logic blocks. The test vector and configuration generation complexity of this method is very small. As presented in the paper, less than 20 test configurations are required in order to detect all the faults, more than 100 billion, for the largest design mapped into the largest commercially available FPGA device, achieving 100% fault coverage.