Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
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Evolutions in process design techniques have allowed the construction of atomic-scale structures like nanowires. These 10nm wires can be used in the construction of regular structures with stochastic assemble, and promise to have up to 2 orders of magnitude greater density when compared to advanced CMOS FPGAs build close to 20nm technology. On the other hand, cost-effective fabrication of nanowires demands a bottom-up approach. In other to characterize the wires, the present wire-by-wire test procedure calls for long test time due to the high number of wires that have to be tested. This way, this paper revises some test strategies and characterization procedures for nanowires imposed by the bottom-up approach, and proposes a new approach, based on the number of wires required to build logic gates and the component granularity in the final circuit to reduce the test and characterization time. Results show meaningful reduction of the test and characterization time when comparing the proposed approach with the wire-to-wire granularity approach. The work here presented proposes a new paradigm of test that bypasses the test and characterization procedures and goes right trough the programming phase. The test at the gate level is performed only after the programming phase We compare our results with the theoretical minimum that could be achieved for XOR gates.