Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The use of nanoscale channel MOSFETs as a candidate for future nonvolatile memory is extensively investigated. The device consists of a wire channel MOSFET with nanometer dimensions on which Si nanocrystals (Si-NCs) are deposited. The memory characteristics as a function of the channel widths for different channel lengths are presented. The channel length dimensions are defined between 100-1000 nm by electron beam lithography and the width dimensions are reduced from a few tens of nanometers down to sub-5 nm by wet etching and thermal oxidation processes. It is found that the controllability of the fabrication process is enhanced as the channel length is reduced to 100 nm. Moreover, memory performances are improved with decreasing channel width due to the bottleneck effect. These results show that the Si-NCs memory is highly scalable in terms of the channel size. In the narrowest channel devices, i.e., in the sub-5-nm range, coulomb-blockade oscillations are obtained due to the ultra-small regions formed in the channel. In such devices, a strong enhancement of the retention characteristics has been found as a result of the quantum mechanical narrow channel effect in the ultra-narrow channel.