Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Proceedings of the 33rd annual international symposium on Computer Architecture
Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Characterization of CA rules for SACA targeting detection of faulty nodes in WSN
ACRI'10 Proceedings of the 9th international conference on Cellular automata for research and industry
An Efficient Test Design for Verification of Cache Coherence in CMPs
DASC '11 Proceedings of the 2011 IEEE Ninth International Conference on Dependable, Autonomic and Secure Computing
Directory based cache coherence verification logic in CMPs cache system
Proceedings of the First International Workshop on Many-core Embedded Systems
Design and Optimization of Traffic Balance Broker for Cloud-Based Telehealth Platform
UCC '13 Proceedings of the 2013 IEEE/ACM 6th International Conference on Utility and Cloud Computing
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This work proposes an efficient test design for verification of cache coherence in CMPs (Chip Multiprocessors). It ensures data coherence more accurate and reliable in a system with thousands of on-chip processors realizing MESI protocol. The design is based on the modular structure of Cellular Automata (CA), a modeling tool invented by von Neumann. A special class of CA referred to as SACA has been introduced to identify the inconsistencies in cache line states of processors' L1 caches. Introduction of segmented CA ensures better efficiency in the design, in terms of number of computations, to detect an inconsistency.