An efficient test design for CMPs cache coherence realizing MESI protocol
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Directory based cache coherence verification logic in CMPs cache system
Proceedings of the First International Workshop on Many-core Embedded Systems
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The data coherence in the cache systems of CMPs with thousands of processors are to be more accurate and reliable. This work proposes an effective solution to address this issue through introduction of highly efficient test logic with the cache controller. It is based on the modular structure of Cellular Automata (CA) and a special class of CA referred to as the SACA (single length single cycle attractor CA) has been introduced to identify the inconsistencies in cache line states of the processors' private caches. The hardware implementation of the proposed test logic can ensure quick verification of cache inconsistencies in CMPs. The proposed design eliminates the requirement of huge storage as well as the complex data structures commonly used to verify the data coherency in a multiprocessor system.