Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Electrical and optical clock distribution networks for gigascale microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Clock distribution in the multi-gigahertz range is getting increasingly difficult due to more stringent requirements for skew and jitter on one hand and the deteriorating supply voltage integrity and process variation on the other hand. Global clock network, especially in nanometer CMOS designs with ever increasing die sizes, has become a prominent performance limiter. A potential alternative to traditional interconnect technology for achieving clock distribution beyond 10 GHz while maintaining required skew and jitter budgets is using on-chip optical interconnects. A practical on-chip optical clocking system must be CMOS compatible in order to provide attractive cost effectiveness for system level integration and ease of manufacturing. This paper presents the design of a fully CMOS compatible optical clock distribution and recovery system in a 3.3 V, 0.35-µm CMOS process. Experimental results from the test chip prove the feasibility of providing optical-electrical interface in devices and circuits in a fully CMOS compatible manufacturing environment. Although the test chips were designed in a mature CMOS process technology and the measured performance is low, the test chips demonstrated the feasibility of on-chip optoelectronic integration with fully CMOS compatible process. On-chip optical clock distribution is one of the natural applications of fully CMOS compatible on-chip optical interconnect technology.