IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Picosecond imaging circuit analysis
IBM Journal of Research and Development
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Fully CMOS-compatible on-chip optical clock distribution and recovery
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On identifying additive link metrics using linearly independent cycles and paths
IEEE/ACM Transactions on Networking (TON)
On testing timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
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With each successive technology generation, process and environmental variations consume an increasingly large portion of the design envelope. To mitigate the impact of these variations, designs can incorporate adaptive techniques to reduce the impact. At the core of adaptability is the fundamental idea that each piece of silicon is different and will respond differently to stimuli. This poses a significant challenge in testing the product because testing relies on all parts behaving in a predictable manner every time they are tested. This article details adaptive techniques used on a dual-core, 90-nm Itanium microprocessor, and the issues and limitations encountered when testing this design.