Modeling and Simulation of Time Domain Faults in Digital Systems

Authors:
D. Barros Junior;F. Vargas;M. B. Santos;I. C. Teixeira;J. P. Teixeira
Affiliations:
PUCRS, Porto Alegre, Brazil;PUCRS, Porto Alegre, Brazil;IST / INESC-ID Lisboa, Portugal;IST / INESC-ID Lisboa, Portugal;IST / INESC-ID Lisboa, Portugal
Venue:
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Year:
2004

Citing 0
Cited 2

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Abstract

In this paper, we propose a novel on-chip circuit to measurethe jitter present at the output of Phase-Locked-Loops(PLLs) used for synthesizing a clock with equal or higherfrequency than the input clock.This measure is performedat every period of the ...