IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a monitor able to detect on-line excessive Power Supply Noise (PSN) at the power/ground lines. It has high resolution (100 ps), enough to collect the important features of PSN and its output is isolated from the local PSN. It is useful for any scheme that takes corrective actions to prevent signal integrity faults after detection of excessive PSN.