Power Supply Noise Monitor for Signal Integrity Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
On-chip measurements complementary to design flow for integrity in SoCs
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents measured results of dynamic voltage drop caused by pulse and periodic injection of spot noise. The test structure being fabricated by a 45 nm low-power process has 1024 delay probes to measure spatial distributions in response to the spot-noise generation. The test structure is the advanced version of our predecessor being fabricated by a 65-nm node, and can trace changes in the spatial distributions with time after the noise injection. The measured results are compared with SPICE simulations, in which package/socket LCR as well as power-line RC within the die is modeled. It is found that the simple model agrees well with the measured results.