CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
BEOL variability and impact on RC extraction
Proceedings of the 42nd annual Design Automation Conference
Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS Technology
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Multi-layer interconnect performance corners for variation-aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Interconnect parasitics are dominating circuit performance,signal integrity and reliability in IC design. Copper/low-kprocess effects are becoming increasingly important toaccurately model interconnect parasitics. Even if theinterconnect process profile is accurately represented,approximations in parasitic extraction could cause largeerrors. Typically, researchers and designers have been usingpre-defined set of structures to validate the accuracy ofinterconnect models and parasitic extraction tools. Unlikeindustry benchmarks on circuits such as MCNC benchmarks,no benchmarks exist for interconnect parasitics. This paperdiscusses the issues in accurate interconnect modeling for130nm and below copper/ultra low-k technologies. A set ofbenchmark structures that could be used to validate accuracyand compare parasitic extraction tools is proposed. Siliconresults from 130nm technology are presented to illustrate theusefulness of these benchmarks. Results of application of thesebenchmarks to compare parasitic extraction tools arepresented to demonstrate systematic validation of resistanceand capacitance extraction.