Integration of DFM Techniques and Design Automation

Authors:
Thomas G. Waring;Gerard A. Allan;and Anthony J. Walton
Affiliations:
-;-;-
Venue:
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Year:
1996

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CAD for nanometer silicon design challenges and success

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems

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Abstract

This paper reports the integration of a yield enhancing router within the Alliance design automation environment. The system converts a high level description, using a subset of VHDL, to mask layout. The final layout has been made more robust to spot defects using a number of layout modification strategies within the routing network. The results indicate that these modifications significantly reduce the probability of faults for the device as a whole.