Sleep switch dual threshold voltage domino logic with reduced standby leakage current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Macro-modeling for the compact simulation of single electron transistor using SIMPLORER
Microelectronics Journal
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
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Si metal-oxide-semiconductor field-effect transistor (MOSFET) scaling trends are presented along with a description of today's 0.13-μm generation transistors. Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si MOSFETs