Empirical model-building and response surface
Empirical model-building and response surface
Microwave circuit analysis and amplifier design
Microwave circuit analysis and amplifier design
Microwave transistor amplifiers (2nd ed.): analysis and design
Microwave transistor amplifiers (2nd ed.): analysis and design
Designing simulation experiments: Taguchi methods and response surface metamodels
WSC '91 Proceedings of the 23rd conference on Winter simulation
Statistical optimization and manufacturing sensitivity analysis of 0.18 &mgr;m SOI MOSFETs
Microelectronic Engineering
Quality Engineering Using Robust Design
Quality Engineering Using Robust Design
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
A layout-aware synthesis methodology for RF circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design and Analysis of Experiments
Design and Analysis of Experiments
Microelectronic Engineering
A methodology for concurrent process-circuit optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of statistical design and response surface methods to computer-aided VLSI device design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this work, we implement a computational statistics technique for design optimization of integrated circuits (ICs). Integration of a well-known circuit simulation software and central composite design method enables us to construct a second-order response surface model (RSM) for each concerned constraint. After construction of RSMs, we verify the adequacy and accuracy using the normal residual plots and their residual of squares. The constructed models are further employed for design optimization of current mirror amplifier ICs with 0.18@mm CMOS devices. By considering the voltage gain, cut-off frequency, phase margin, common-mode rejection ratio and slew-rate, six designing parameters including the width and length of different transistors are selected and optimized to fit the targets.