Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing

  • Authors:
  • G. Stehr;H. Graeb;K. Antreich

  • Affiliations:
  • Inst. for Electron. Design Autom., TU Munich, Germany;Inst. for Electron. Design Autom., TU Munich, Germany;Inst. for Electron. Design Autom., TU Munich, Germany

  • Venue:
  • Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
  • Year:
  • 2004

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Abstract

Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel technique for the efficient simulation-based exploration of high-dimensional performance spaces is presented. To this end, fundamental circuit design knowledge is described by constraint functions. Based on a linearization of the latter and of the circuit performance functions, a description of the feasible performance range in the form of a polytope is derived. Moreover, the approach is integrated into a hierarchical sizing method, where it propagates topological and technological constraints bottom-up. Practical application results demonstrate the efficiency and usefulness of the new method.