Analog Integrated Circuits and Signal Processing - Special issue: low-voltage low-power analog integrated circuits
MAELSTROM: efficient simulation-based synthesis for custom analog cells
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An efficient search algorithm to find the elementary circuits of a graph
Communications of the ACM
Symbolic Analysis for Automated Design of Analog Integrated Circuits
Symbolic Analysis for Automated Design of Analog Integrated Circuits
Computer Methods for Circuit Analysis and Design
Computer Methods for Circuit Analysis and Design
The sizing rules method for analog integrated circuit design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ASF: a practical simulation-based methodology for the synthesis of custom analog circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Support vector machines for analog circuit performance representation
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
PAD: A New Interactive Knowledge-Based Analog Design Approach
Analog Integrated Circuits and Signal Processing
Analog Design Centering and Sizing
Analog Design Centering and Sizing
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
CMOS Analog Design Using All-Region MOSFET Modeling
CMOS Analog Design Using All-Region MOSFET Modeling
Structured Analog CMOS Design
Synthesis of high-performance analog circuits in ASTRX/OBLX
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
OASYS: a framework for analog circuit synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
OPASYN: a compiler for CMOS operational amplifiers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DELIGHT.SPICE: an optimization-based system for the design of integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AMGIE-A synthesis environment for CMOS analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A CAD methodology for optimizing transistor current and sizing in analog CMOS design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Operating-point driven formulation for analog computer-aided design
Analog Integrated Circuits and Signal Processing
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A hierarchical sizing and biasing methodology for analog firm intellectual properties (IPs) is presented. An analog firm IP designates an unsized transistor netlist of an analog circuit. The methodology sizes and biases an analog firm IP by automatically generating suitable sizing procedures. The generated procedures respect topology constraints, designer's hypotheses and design constraints. The procedures are represented using dependency graphs. The methodology deals with different aspects of analog design problems such as MOS inversion level control, insufficient or excess design parameters, systematic offset and negative-feedback. Its application in both fields of analog synthesis and simulation is outlined. The proposed methodology has been successfully used to size, bias and analyze two analog IPs: a single-ended two-stage operational amplifier and a fully differential transconductor. This is performed using 130nm CMOS technology with V"D"D=1.2V. The results prove the effectiveness and precision of the proposed methodology.