Application-independent hierarchical synthesis methodology for analogue circuits
EURO-DAC '94 Proceedings of the conference on European design automation
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
ANTIGONE: Top-down creation of analog-to-digital converter architectures
Integration, the VLSI Journal
Analog circuits optimization based on evolutionary computation techniques
Integration, the VLSI Journal
ASLIC: A low power CMOS analog circuit design automation
Integration, the VLSI Journal
Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm
Integration, the VLSI Journal
Hierarchical sizing and biasing of analog firm intellectual properties
Integration, the VLSI Journal
Operating-point driven formulation for analog computer-aided design
Analog Integrated Circuits and Signal Processing
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A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and (3) mask geometry construction using a macro cell layout style. The synthesis process is fast enough for the program to be used interactively at the system design level by system designers who are inexperienced in operational amplifier design