An effective DFM strategy requires accurate process and IP pre-characterization
Proceedings of the 42nd annual Design Automation Conference
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A scalable σ-space based methodology for modeling process parameter variations in analog circuits
Microelectronics Journal
A fast heuristic approach for parametric yield enhancement of analog designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circuits. The main feature of this methodology is that it accounts for device mismatch by using a number of variables that is asymptotically constant in the limit of perfectly matching devices, and is typically close to the number of independent process factors normally used to account for inter-die process variations only. A unified model of process variation allows the effects of each source of variation and their joint impact to be estimated, thus providing designers more accurate analysis and variance optimization capability. State-of-the-art application examples demonstrate the accuracy and efficiency of this approach.