Efficient analog circuit synthesis with simultaneous yield and robustness optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The sizing rules method for analog integrated circuit design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Microelectronic Circuit Design
Microelectronic Circuit Design
Efficient handling of operating range and manufacturing line variations in analog cell synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS op-amp sizing using a geometric programming formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SubIslands: the probabilistic match assignment algorithm for subcircuit recognition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
| Hi-index | 0.00 |
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level of transistor-pair groups. This reduces the effort for and improves the resulting quality of analog circuit synthesis. We present a hierarchical library of transistor-pair groups as basic building blocks for analog bipolar circuits. Sizing rules are constraints associated to these building blocks that must be satisfied to guarantee the function and robustness of each block. Results of applications like circuit sizing or design centering show that the use of sizing rules leads to improved and robust results.