Generalized Simulation-Based Posynomial Model Generation for Analog Integrated Circuits

Authors:
Tom Eeckelaert;Walter Daems;Georges Gielen;Willy Sansen
Affiliations:
Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT–MICAS, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium. tom.eeckelaert@esat.kuleuven.ac.be;Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT–MICAS, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium;Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT–MICAS, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium. georges.gielen@esat.kuleuven.ac.be;Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT–MICAS, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2004

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Abstract

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. Both the coefficient set as well as the exponent set of the posynomial expression, for some performance as a function of the design variables, are determined based on performance data extracted from SPICE simulation results with device-level accuracy. Techniques from design of experiments (DOE) are used to generate an optimal set of sample points to fit the models. We will prove that the optimization problem formulated for this problem typically corresponds to a non-convex problem, but has no local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that can be used to compose a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming nature of hand-crafted analytic model generation. Experimental results illustrate the capabilities of the presented modeling technique.