Generalized Simulation-Based Posynomial Model Generation for Analog Integrated Circuits
Analog Integrated Circuits and Signal Processing
Faster, parametric trajectory-based macromodels via localized linear reductions
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Convex piecewise-linear modeling method for circuit optimization via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Equation-based circuit optimization using geometric programming (GP) is a promising analog and mixed-signal design framework that is inherently capable of hierarchical design synthesis. By taking a dynamic comparator as a test vehicle, this paper presents a reduced-complexity cell-level macromodeling method compatible with equation-based circuit optimization using GP. A key contribution of this paper is the demonstration of the complexity-reduction method in creating a convex, empirical, and cell-level macromodel. The variable space reduction is guided by the 1st-order modeling obtained from fundamental understandings on the circuit behavior. The proposed modeling is ideally applicable to create a macromodel exhibiting nonlinear behaviors in time-domain, which are not readily captured in a traditional equation-based modeling approach. The numerical experiment using a dynamic comparator in 0.13 μm CMOS process as a test vehicle indicates that the modeling errors for major performance metrics are less than 5 %, while obtained Pareto-front tradeoff provides useful design guidelines on the architecture-level design exploration.