Design of pipeline analog-to-digital converters via geometric programming
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Convex Optimization
Generalized Posynomial Performance Modeling
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Digital Circuit Optimization via Geometric Programming
Operations Research
Simulation-based reusable posynomial models for MOS transistor parameters
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A convex macromodeling of dynamic comparator for analog circuit synthesis
Analog Integrated Circuits and Signal Processing
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This paper presents a new method for fitting a convex piecewise-linear function to a given set of data, which can serve as an empirical modeling framework for circuit optimization via geometric programming. The method iteratively solves a series of linear optimization problems to minimize the fitting error. To reduce the fitting error in each iteration, an extra plane is added in the region where the largest error occurs. For verification, we apply the method to create transistor-level models in 90-nm complementary metal-oxide-semiconductor technology. Numerical results indicate that the proposed method can generate process-dependent transistor-level models with reasonable modeling accuracy.