Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist

Authors:
Shuenn-Yuh Lee;Chih-Yuan Chen;Jia-Hua Hong;Rong-Guey Chang;Mark Po-Hung Lin
Affiliations:
Department of Electrical Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;Department of Computer Science and Information Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;Department of Electrical Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;Department of Computer Science and Information Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;Department of Electrical Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan
Venue:
Microelectronics Journal
Year:
2011

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Abstract

A synthesis tool consisting of coefficient synthesis of architecture, circuit specifications synthesis, and CMOS operational-amplifier (op-amp) synthesis for discrete-time sigma-delta modulators (SDMs) is presented. In circuit specifications synthesis, several major circuit non-idealities are discussed and modeled. A precise performance prediction with a new design flow of specification synthesis is proposed. A hybrid design methodology composed of equation-based and simulation-based approaches for synthesizing fully differential two-stage and folded-cascode op-amps in 0.35@mm technology is also presented. Experimental results show that the peak signal-to-noise and distortion ratio (PSNDR) of the fourth-order feed-forward (FF) SDM with an oversampling ratio (OSR) of 64 and a bandwidth of 20KHz estimated by the proposed synthesis tool is 94.19dB, and the result of the circuit simulation with folded-cascode op-amp is 93.03dB. The estimated PSNDR of the third-order multiple-feedback (MF) SDM with an OSR of 32 and a bandwidth of 256KHz is 59.52dB, and the HSPICE simulation result is 55.39dB.