DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cross-Coupled Noise Propagation in VLSI Designs
Analog Integrated Circuits and Signal Processing
Efficient Model Update for General Link-Insertion Networks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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In this paper we presen t a rank-one update method for updating reduced-order models of interconnect parasitics when driv e resistances or load capacitances change, as commonly occurs during timing analysis. These rank-one updates are extremely inexpensive, do not require reexamining the original in terconnect netw ork, and most importantly are provably equivalent to rereducing the original netw ork. This abstract con tains the proof only for the case of varying the driver resistance, but examples are given to show that the exactness holds more generally. In particular, a cross-talk case is examined where the conductance matrix is singular.