Latch modeling for statistical timing analysis

Authors:
Sean X. Shi;Anand Ramalingam;Daifeng Wang;David Z. Pan
Affiliations:
University of Texas, Austin TX;University of Texas, Austin TX;University of Texas, Austin TX;University of Texas, Austin TX
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

Citing 12
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Abstract

Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new latch delay model in the context of SSTA based on a new perspective of latch timing. The proposed latch model also takes into account the external timing variations such as data slew. The new latch model is integrated into SSTA by considering the timing analysis of both the combinational logic network and the clock distribution network simultaneously. The experimental results show that ignoring accurate latch modeling may lead to large errors (e.g., 50% at PDF peak).