Timing margin evaluation with a simple statistical timing analysis flow

  • Authors:
  • V. Migairou;R. Wilson;S. Engels;Z. Wu;N. Azemard;P. Maurine

  • Affiliations:
  • STMicroelectronics Design Department 850 rue J. Monnet, 38926, Crolles, France;STMicroelectronics Design Department 850 rue J. Monnet, 38926, Crolles, France;STMicroelectronics Design Department 850 rue J. Monnet, 38926, Crolles, France;LIRMM, UMR CNRS/Université de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France;(Correspd. E-mail: nadine.azemard@lirmm.fr) LIRMM, UMR CNRS/Université de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France;LIRMM, UMR CNRS/Université de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France

  • Venue:
  • Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
  • Year:
  • 2009

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Abstract

With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important. One way to mitigate these effects is to ensure uniform switching of bus wires. This prevents the unusual heating ...