Nutcracker: an efficient and intelligent channel spacer

Authors:
X.-M. Xiong;E. S. Kuh
Affiliations:
Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Berkeley, CA;Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Berkeley, CA
Venue:
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Year:
1987

Citing 4
Cited 7

Routing L-shaped channels in nonslicing-structure placement

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A dynamic and efficient representation of building-block layout

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Plane-sweep algorithms for intersecting geometric figures

Communications of the ACM

Object oriented Lisp implementation of the CHEOPS VLSI floor planning and routing system

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic layout compaction review

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
How to obtain more compactable channel routing solutions

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Improved channel routing by via minimization and shifting

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Optimal via-shifting in channel compaction

EURO-DAC '90 Proceedings of the conference on European design automation
CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP

EURO-DAC '90 Proceedings of the conference on European design automation

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new algorithm for channel spacing is discussed in this paper. In contrast to existing compaction algorithms, we rely on the geometric method and bypass the constraint graph during the whole spacing process.We propose an efficient way to enumerate all possible jogs. Therefore, for the given channel routing topology, our algorithm yields the minimal channel height with the incorporation of contacts sliding and automatic jog insertion. In the final output, only necessary jogs are inserted, and the total wire length is minimized.