An optimal chip compaction method based on shortest path algorithm with automatic jog insertion

• Authors:

• Toru Awashima;Wataru Yamamoto;Masao Sato;Tatsuo Ohtsuki

• Affiliations:

• Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan;Central Research Lab., Hitachi Ltd. and Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan;Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan;Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan

• Venue:
• ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
• Year:
• 1992